For more information on using external clocks, timing specifications for using on-chip RAM or external ROM, please refer to the "Targeting Hardware" section in the Handel-C language reference book/pdf.A brief description of Off-Chip interfaces: reading from external pins etc, is included. For more detailed descriptions please refer to the "Targetting Hardware" section in hte Handel-C language reference book/pdf.
In order to target a specific FPGA, the compiler must be supplied with the FPGA part number. Ultimately, this information is passed to the FPGA place and route tool to inform it of the device it should target.
The syntax for targeting devices consists of two parts - the target family and the target part. The general syntax is:
set family = Family;
set part = Part Number;Recognised families are :
Family Name DescriptionAltera6K Flex6K series Altera FPGAs Altera8K Flex8K series Altera FPGAs Altera10K Flex10K series Altera FPGAs Virtex Virtex series Xilinx FPGA Xilinx3000 3000 series Xilinx FPGAs Xilinx4000 4000 series Xilinx FPGAs Xilinx4000A 4000A series Xilinx FPGAs Xilinx4000D 4000D series Xilinx FPGAs Xilinx4000H 4000H series Xilinx FPGAs Xilinx4000E 4000E series Xilinx FPGAs Xilinx4000L 4000L series Xilinx FPGAs Xilinx4000EX 4000EX series Xilinx FPGAs Xilinx4000XL 4000XL series Xilinx FPGAs Xilinx4000XV 4000XV series Xilinx FPGAs The Part Numberis the complete Xilinx or Altera device string.
For example:
set family = Xilinx4000E;
set part = “4010EPC84-1”;
or for Virtex parts
set family = Xilinx4000XV; // Covers virtex parts as well
set part = "V1000BG560-4";This instructs the compiler to target a XC4010E device in a PLCC84 package. It also specifies that the device is a -1 speed grade. This last piece of information is required for the timing analysis of your design by the Xilinx tools. The family is used to inform the compiler of which special blocks it may generate. The Xilinx3000 family covers all Xilinx 3000 devices with any suffix.
To target Altera devices:
set family = Altera10K;
set part = “EPF10K20RC240-3”;This instructs the compiler to target an Altera Flex 10K20 device in a RC240 package. It also specifies that the device is a -3 speed grade. This last piece of information is required for the timing analysis of your design by the Altera Max Plus II tools. Note that when performing place and route on the resulting design, the device and package must also be selected via the menus in the Max Plus II software. Refer to chapter 4 in the Compiler Reference Manual for further details of selecting FPGA part numbers.
All off-chip interfaces other than RAMs are declared with the interface keyword. The general syntax of interfaces is as follows:
interface
Sort(Types) Name(Args) with {Specs};
Sort field specifies what sort of interface is required.
Types describes the types of values associated with objects coming from the interface.
Name specifies an identifier for the interface.
Args specifies any parameters that the interface may require.
Specs give hardware details of the interface such as chip pin numbers.Handel-C currently provides the following interface sorts:
Type Identifier Descriptionbus_in
Input bus from pins bus_latch_in
Latched input from pins bus_clock_in
Clocked input bus from pins bus_out
Output bus to pins bus_ts
Bi-directional tri-state bus bus_ts_latch_in
Bi-directional tri-state bus with latched input bus_ts_clock_in
Bi-directional tri-state bus with clocked input
Six methods for reading from external pins exist. Buses declared as input or bi-directional are capable of reading from external pins. Three sort of input buses can be declared; an asynchronous input bus, a latched input bus and a clocked input bus. Bi-directional buses are detailed in the section entitled Bi-directional data transfers to external pins.
Asynchronous bus: bus_in
The
bus_in
interface sort allows Handel-C programs to read from external pins. Its general usage is:
interface bus_in(Type) Name() with {data = {Pin List}};
A specific example might be:
interface bus_in(int 4) InBus() with
{data = {“P1”, “P2”, “P3”, “P4”}};This declares a bus connected to pins P1, P2, P3 and P4 where pin P1 is the most significant bit and pin P4 is the least significant bit. Reading the bus is performed by accessing the identifier Name.in as a variable which will return the value on those pins at that clock edge.
For example:
int 4 x;
x = InBus.in;This sets the variable x to the value on the external pins. The type of InBus.in is int 4 as specified in the type list after the bus_in keyword.
Clocked and Latched buses: bus_latch_in, bus_clock_in
The
bus_latch_in
interface sort is similar to thebus_in
interface sort but allows the input to be latched on a condition. This may be required to sample the signal at particular times.
Thebus_clock_in
interface sort is similar to thebus_in
interface sort but allows the input to be clocked continuously from the Handel-C global clock.
Their general usage is:
interface bus_latch_in(Type) Name(Condition) with {data = {Pin List}};
interface bus_clock_in(Type) Name() with {data = {Pin List}};Bus_latch_in usage is exactly like the bus_in interface sort except that Condition specifies a signal that is used to clock the input latches in the FPGA. The rising edge of this signal clocks the external signal to the internal value.
Bus_clock_in usage is exactly like thebus_in
interface sort. The rising edge of the Handel-C clock clocks the external signal to the internal value.
For example:
int 1 get;
int 4 x;
interface bus_latch_in(int 4) InBus(get) with
{data = {“P1”, “P2”, “P3”, “P4”}};
interface bus_clock_in(int 4) InBus2() with
{data = {“P1”, “P2”, “P3”, “P4”}};
get = 0;
get = 1; // Latch the external value
x = InBus.in; // Read the latched value
x = inBus2.in; // Read the clock latched value
bus_out
The
bus_out
interface sort allows Handel-C programs to write to external pins. Its general usage is:
interface bus_out() Name(Expression) with {data = {Pin List}};
A specific example might be:
interface bus_out () OutBus(x+y) with
{data = {“P1”, “P2”, “P3”, “P4”}};This declares a bus connected to pins 1, 2, 3 and 4 where pin 1 is the most significant bit and pin 4 is the least significant bit. The value appearing on the external pins is the value of the expression
x + y
at all times.
Three forms of bi-directional transfers exist; an asynchronous sort, a clocked and a latched sort.
Asynchronous bi-directonal transfers: bus_ts
The
bus_ts
interface sort allows Handel-C programs to read or write from external pins. Its general usage is:
interface bus_ts (Type) Name(Value, Condition)
with {data = {Pin List}};Here, Value and Condition are two expressions. Value refers to the value to output on the pins and Condition refers to the condition for driving the pins. When the second expression is non-zero (i.e. true), the value of the first expression is driven on the pins. When the value of the second expression is zero, the pins are tri-stated and the value of the external bus can be read using the identifier Name.in in much the same way that
bus_in
interfaces work.
A specific example might be:
int 1 enable;
int 4 x;
interface bus_ts(int 4) BiBus(x+1, enable==1)
with {data = {“P1”, “P2”, “P3”, “P4”}};
enable = 0; // Tri-state the pins
x = BiBus.in; // Read the value
enable = 1; // Drive x+1 onto the pinsThis example reads the value of the external bus into variable x and then drives the value of
x + 1
onto the external pins. The type ofBiBus.in
is int 4 as specified in the type list after thebus_ts
keyword.Clocked and Latched bi-directional transfers: bus_ts_clock_in, bus_ts_latch_in
Bi-directional latched and clocked transfers can be declared as:
interface bus_ts_latch_in (Type) Name(Value, Condition, Clock)
with {data = {Pin List}};
interface bus_ts_clock_in (Type) Name(Value, Condition)
with {data = {Pin List}};
Take care when driving tri-state buses that the FPGA and another device on the bus cannot drive simultaneously as this may result in damage to one or both of them.