RC1000-PP Host: Clocking Functions


PP1000SetClockRate


  PP1000_STATUS PP1000SetClockRate(
                      PP1000_HANDLE Card,
                      PP1000_CLOCK Clock,
                      double Rate);
  

 

Arguments
Card Handle of card to set clock on.
Clock Identifier of clock to program.
Rate Frequency (in Hertz) to set clock to.
Return Values
PP1000_SUCCESS Success.
PP1000_INVALID_HANDLE Card is not valid card handle.
PP1000_INVALID_CLOCK_RATE Rate is out of range.
PP1000_INVALID_CLOCK Clock is invalid.
PP1000_INTERNAL_ERROR Error while talking to driver.
Description

This function is used program one of the clocks on a card. The value of Clock can be either PP1000_MCLK or PP1000_VCLK.

When the Clock parameter is set to PP1000_MCLK, the MCLK input is set to the frequency specified by the Rate parameter provided that JP2 is linking positions 2 and 3. When JP2 is in positions 1 and 2, the MCLK pin is fed from the clock in connector (J10). Refer to the hardware reference manual for further details of jumper settings.

When the Clock parameter is set to PP1000_VCLK, the VCLK input is set to the frequency specified by the Rate parameter provided that JP3 is linking positions 2 and 3. When JP3 is in positions 1 and 2, the VCLK pin is fed from the local PCI bus clock. (Set at 33MHz.) Refer to the hardware reference manual for further details of jumper settings.

Setting the Rate of VCLK will automatically start the clock running. Refer to the PP1000StopVClock() function for details of how to stop the signal on the VCLK pin.

The value of Rate can be anything between 400kHz (4x10e5 ) and 100MHz (1x10e8 ). The clock will be set to the closest obtainable frequency.

The value of Card is obtained from a call to one of the initialisation functions, PP1000OpenCard() or PP1000OpenFirstCard().

You should avoid setting the MCLK and VCLK outputs from the clock generator to frequencies which are close together to avoid noise on the clock.

 

 

PP1000StartVClock


  PP1000_STATUS PP1000StartVClock(
                      PP1000_HANDLE Card);

 

Arguments
Card Handle of card to set clock on.
Return Values
PP1000_SUCCESS Success.
PP1000_INVALID_HANDLE Card is not valid card handle.
PP1000_INTERNAL_ERROR Error while talking to driver.
Description

This function is used start the signal on the VCLK input of the FPGA provided that JP3 is linking positions 2 and 3. When JP3 is in positions 1 and 2, the VCLK pin is fed from the local PCI bus clock which is set at 33MHz. Refer to the hardware reference manual for further details of jumper settings.

When the VCLK signal is started, it will return to the rate set by the last call to PP1000SetClockRate() with a parameter of PP1000_VCLK..

The value of Card is obtained from a call to one of the initialisation functions, PP1000OpenCard() or PP1000OpenFirstCard().

 

 

PP1000StepVClock

 
  PP1000_STATUS PP1000StepVClock(
                      PP1000_HANDLE Card);
 

 
Arguments
Card Handle of card to set clock on.
Return Values
PP1000_SUCCESS Success.
PP1000_INVALID_HANDLE Card is not valid card handle.
PP1000_INTERNAL_ERROR Error while talking to driver.
Description

This function is used to single step the signal on the VCLK input of the FPGA provided that JP3 is linking positions 2 and 3. When JP3 is in positions 1 and 2, the VCLK pin is fed from the local PCI bus clock which is set at 33MHz. Refer to the hardware reference manual for further details of jumper settings.

Before the VCLK pin can be single stepped, it must be stopped with a call to PP1000StopVClock().

The value of Card is obtained from a call to one of the initialisation functions, PP1000OpenCard() or PP1000OpenFirstCard().

 

PP1000StopVClock

  
  PP1000_STATUS PP1000StopVClock(
                      PP1000_HANDLE Card);
  

 

Arguments
Card Handle of card to set clock on.
Return Values
PP1000_SUCCESS Success.
PP1000_INVALID_HANDLE Card is not valid card handle.
PP1000_INTERNAL_ERROR Error while talking to driver.
Description

This function is used stop the signal on the VCLK input of the FPGA provided that JP3 is linking positions 2 and 3. When JP3 is in positions 1 and 2, the VCLK pin is fed from the local PCI bus clock which is set at 33MHz. Refer to the hardware reference manual for further details of jumper settings.

When the VCLK signal is stopped, it will be held high until either the PP1000StartVClock() or PP1000SetClockRate() function is called.

The value of Card is obtained from a call to one of the initialisation functions, PP1000OpenCard() or PP1000OpenFirstCard().